Integrated Systems for Digital Signal Processing
Code: 45644Credits: 6
| Degree programme | Type | Course |
|---|---|---|
| Telecommunication Engineering | OB | 1 |
Contact lecturer
- Name :
- Jordi Carrabina Bordoll
- Email :
- jordi.carrabina@uab.cat
Teaching staff
- Waldo Nogueira Vazquez
- Albert Alvarez Carulla
- Stepan Sutula Grinchenko
Group languages
You can consult this information at the end of the document.
Prerequisites
Previous elementary knowledge on SystemVerilog (evolution from Verilog) Hardware Description Languages is required. For those students that don’t have these minimal skills, we will offer complementary sessions prior to the starting of the course either face-2-face (to be scheduled) or on-line (e.g. part of https://www.cadence.com/en_US/home/training/all-courses/82143.html).
Knowledge of the following subjects is recommended:
Digital Signal Processing
Digital Design
Electronic Systems and Applications
Objectives
The main objective of this course is to learn, understand and be able to design digital electronic systems for digital signal processing with the focus on integrated systems. These systems are composed of digital modules that manage their computation and communication. This course tries to cope with the 3 main design levels: (1) system application level; (2) specification, modelling and verification using hardware description languages; and (3) physical implementation in HW platforms (FPGAs) and advanced technology nodes (ASICs). Each level will have a different experienced teacher.
The course relies on common digital signal processing architectures using an application on acoustics,speech processing and hearing devices to demonstrate the digital design flow from application to implementation.
For that purpose, different industry-grade design methodologies will be adopted for every level of abstraction (system-level, logic-level, physical-level)
SystemVerilog HDL will be used to prototype such systems in the labs on electronic boards with FPGA reconfigurable devices for its real time implementation.
Learning outcomes
- (CA12) Correctly assess hardware design tools, using hardware description languages, and SW necessary to implement digital processing algorithms in microelectronic platforms such as programmable logic devices (FPGA, eFPGA, CPLD).
- (CA13) Examine the system-level requirements (functional and cost, speed, and energy presentations) in the implementation chain of digital signal processing algorithms and apply techniques to correct unwanted deviations.
- (CA14) Use digital signal processing knowledge in commercial microelectronic technologies and solutions in different application fields such as telemedicine, bioengineering and robotics in professional and academic fields
- (CA15) Create, advanced digital signal processing algorithms, using current methodologies and tools in multidisciplinary environments.
- (KA13) Describe the operation and organisation of hardware components, intermediary software and digital signal processing applications.
- (KA14) Identify applications based on media signal processing and associated business models.
- (KA15) Use advanced knowledge to develop original ideas in solving digital signal processing problems.
- (SA20) Apply signal processing methods using hardware description languages (HDL) models and languages for digital implementation at different levels of abstraction: system, modular and physical implementation.
- (SA21) Design the hardware and software components of systems-on-a-chip (SoC) integrated circuits for implementation in today's microelectronic technologies.
- (SA22) Model complex digital systems using design tools and workflows taking into account the functional and performance constraints of the system.
Contents
0. Introduction to Integrated Systems for Digital Signal Processing
Chip Design Methodologies for ASIC and FPGA.
Fundamentals of Digital Signal Processing (Quantization, Sampling, Z-transform, Filter design, Digital Fourier Transform)
1. High-level Digital Signal Processing and its Adaptation for Integration
Introduction to Acoustics, Spatial Audio, Speech Sounds and Speech Processing
Source Filter Models & Speech Coding
Asynchronous sample rate conversion (ASRC) and Real time low latency processing (circular buffers)
Optimization of (Fast Fourier Transform – Radix algorithms)
Floating point to Fixed Point conversion Algorithms
2. Systems-on-a-Chip Design Methodologies
Modular digital design: Virtual Components (IPs) and its connectivity
SystemVerilog for HDL Modelling and synthesis
Verification techniques: HDL simulation, timing analysis, Hardware-in-the-loop (HIL), HW/SW co-simulation.
3. Deployment on Integrated Systems
Chip structure: ASICs & FPGAs
Power Performance Analysis (PPA): area, speed & Energy
Clock and Power Management
Prototyping and industrialization
Laboratories: Real-time Audio Digital Signal Processing on FPGA
Learning activities and methodology
| Title | Hours | ECTS | Learning outcomes |
|---|---|---|---|
| Type: Autonomous | |||
| Laboratory preparation and reporting | 30 | 1.2 | CA12, CA15, KA13, KA15, SA20, SA21, SA22 |
| Study | 56 | 2.24 | CA12, CA13, CA14, CA15, KA13, KA14, KA15, SA20, SA21, SA22 |
| Type: Guided | |||
| Laboratory Sessions | 15 | 0.6 | CA12, CA13, CA14, CA15, KA15, SA20, SA21, SA22 |
| Lectures | 30 | 1.2 | CA12, CA13, CA14, CA15, KA13, KA14, KA15, SA21, SA22 |
| Type: Supervised | |||
| Thematic Homework (Individual) | 15 | 0.6 | CA12, CA13, CA14, KA13, KA15, SA20 |
The course will be mainly driven by the lectures, which will use ad hoc material (presentations, documents, links, tools and other resources) available in the virtual campus (VC) of the UAB (https://cv.uab.cat). Students will deliver exercises on specific subjects (on the Virtual Campus).
As a new common policy at UAB, generative AI tools will be allowed while the students must add the tool name and the used prompts. The focus on its evaluation will extend to the entire development process with potential follow-up interviews.
Laboratory work will let the students to apply and experiment with the concepts acquired on FPGA platforms, widely used in industry. In the case of the labs, the AI tools are not allowed at the classroom since they usually make serious errors for unexperienced users, especially when coding SystemVerilog. Specially for the labs, we expect that master students prepared them before the on-site session. Attendance will be mandatory for all sessions. Any lack of attendance must be communicated in advance to the teacher in charge, attaching the corresponding reasonable justified reasons.
Annotation: Within the schedule set by the center or master program, 15 minutes of one class will be reserved for students to evaluate their lecturers and their courses or modules through questionnaires.
Assessment
Continuous assessment activities
| Title | Weight | Hours | ECTS | Learning outcomes |
|---|---|---|---|---|
| Inidividual Exercises | 15% | 0 | 0 | CA13, CA14, KA13, KA14, KA15, SA20, SA22 |
| Laboratory work follow-up & reports | 35% | 0 | 0 | CA12, CA13, CA14, CA15, SA20, SA21, SA22 |
| Partial Evaluación (Part 1): Exam | 25% | 2 | 0.08 | CA12, CA13, CA14, KA14, SA22 |
| Partial Evaluación (Part 2): Exam | 25% | 2 | 0.08 | CA12, CA13, KA13, KA14, SA20, SA21, SA22 |
This course does not provide a single assessment evaluation (only 1 exam exam).
Student assessment uses continuous evaluation made up of the following assessments:
• Two partial exams for each part of the course, which gives 25% of the final grade.
• Individual work in thematic exercises (delivered on the virtual campus), which accounts for 15% of the final grade
• Teamwork in the laboratory, scheduled in 5 sessions, for which they have to deliver the corresponding reports. This activity contributes 35% to the final grade of the course. An evaluation above 5 is mandatory to pass the course. Specially during the labs, the teacher will evaluate the skill, development and correctness of the preparation and results of every lab during the classroom.
The final exam allows students to assess the achievement of skills in a single exam or to recover any partial assessments that had a mark lower than 4. That is also the minimum mark required for any of the parts to pass the course and the average mark of both exams is not below 5.
A weighted final grade of not lower than 5 is required to pass the course.
To obtain MH, students will need to have an overall qualification higher than 8.5 with the limitations of the UAB (1 MH/10 students). As a reference criterion, they will be assigned in descending order.
Plagiarism will not be tolerated either in exams or in individual activities on the Virtual Campus. In this case, the available tools will be used to verify it. All students involved in plagiarism will be automatically suspended. A final grade of no more than 30% will be assigned.
Open-source code or available libraries can be used but they must be referred in the corresponding reports.
The student will receive a grade of "Not Evaluable" if:
- the student has not been able to be evaluated in the laboratory due to not attendance or not deliver the corresponding reports without justified cause.
- the student has not carried out a minimum of 50% of the activities proposed.
- the student has not taken the final exam.
Repeating students will be able to “save” their grade in lab but not in the rest of the activities.
Bibliography
Digital Speech Processing
• Peter Vary, Rainer Martin, Digital Speech Transmission: Enhancement, Coding and Error Concealment, John Wiley & Sons Inc, 2006. (New issue to appear during 2024).
• L.R. Rabiner and W. Schafer. 2007. Introduction to digital speech processing. http://cronos.rutgers.edu/~lrr/dsp%20design%20course/final_speech_paper_1_2008.pdf
• Xuedong Huang, Alex Acero, Hsiao-Wuen Hon, Spoken Language Processing: A Guide to Theory, Algorithm, and System Development, ISBN: 0130226165, Prentice Hall, 2001.
SoC Design & HDL
• Chakravarthi, V.S. A practical approach to VLSI system on chip (SoC) design: a comprehensive guide [on line]. Cham: SpringerCham,2020. Available at: https://link-springer-com.recursos.biblioteca.upc.edu/book/10.1007/978-3-030-23049-4. ISBN 9783030230494.
• P. Bricaud, M. Keating : “Reuse Methodology Manual for System-On-A-Chip Designs”
• Spear, C.; Tumbush, G. SystemVerilog for verification: a guide to learning the testbench language features [on line]. 3rd ed. New York,NY: Springer, 2012. Available at: https://link-springer-com.recursos.biblioteca.upc.edu/book/10.1007/978-1-4614-0715-7. ISBN 9781461407157.
• Vaibbhav Taraate, Digital logic design using Verilog : coding and RTL synthesis, Springer, ISBN 978-981-16-3198-6, 2022. Available at on-line through your UAB account https://bibcercador.uab.cat/
• Mehta, A.B. ASIC/SoC functional design verification [on line]. Springer, 2017 [Consultation: 11/06/2024]. Available on: https://link-springer-com.recursos.biblioteca.upc.edu/book/10.1007/978-3-319-59418-7. ISBN 9783319594187.
• Wile, B.; Goss, J.C.; Roesner, W. Comprehensive functional verification: the complete industry cycle [on line]. Elsevier/MorganKaufmann, 2005.Available at: https://ebookcentral-proquest-com.recursos.biblioteca.upc.edu/lib/upcatalunya-ebooks/detail.action?pqorigsite=primo&docID=234976. ISBN 9780080476643.
Integrated and Embedded Systems:
• Edward A. Lee and Sanjit A. Seshia, Introduction to Embedded Systems, A Cyber-Physical Systems Approach, Second Edition, MIT Press, ISBN 978-0-262-53381-2, 2017.Available at https://ptolemy.berkeley.edu/books/leeseshia/releases/LeeSeshia_DigitalV1_08.pdf
• I. Grout “Digital Systems Design with FPGAs and CPLDs”
• H.J.M. Veendrick “Nanometer CMOS: from ASICS to BASICS”, 2ª edición, Springer. 2017. Available at on-line through your UAB account https://bibcercador.uab.cat/
Software
Students will use two main high level signal processing tools:
- Application Specific tools for recording (smartphone or PC with microphone), plus Audacity SW to edit the sounds (http://audacity.sourceforge.net/) and PRAAT (http://www.fon.hum.uva.nl/praat/) as speech processing tool including a great variety of integrated functions
- Matlab/Simulink as a general-purpose platform for model building, transformation and generation of the hardware descriptions of the systems to implement.
The electronic design tools (EDA) associated with Altera FPGA boards used in laboratories that enable:
- Specification of digital systems in HDL languages
- Building SoC architectures for RISC processors (ARM, NIOS)
- Logical and physical synthesis of HDL
- Downloading HW and SW code from the PC to the FPGA
- Execution of the algorithm in the FPGA
Altera's DE1_SoC board will be used as the SoC-FPGA platform.
Students will have free access, upon request, to courses on industrial EDA tools (CADENCE) useful for their curriculum and training, mainly for subjects 4 and 5.
https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/training/learning-maps.pdf
Course groups and languages
The information provided is provisional until November 30. After this date, you will be able to consult the language of each group through this link. To access the information, you will need to enter the course CODE
| Type of teaching | Group | Language | Semester | Shift |
|---|---|---|---|---|
| (TEmRD) Teoria (màster RD) | 1 | English | second semester | afternoon |
| (PLABmRD) Pràctiques de laboratori (màster RD) | 1 | English | second semester | afternoon |