Electronic Systems Design
Code: 102723Credits: 6
| Degree programme | Type | Course |
|---|---|---|
| Electronic Engineering for Telecommunication | OB | 3 |
Contact lecturer
- Name :
- Raimon Casanova Mohr
- Email :
- raimon.casanova@uab.cat
Group languages
You can consult this information at the end of the document.
Prerequisites
It is recommended to have passed the subjects of the first year of programming and have taken the second year course on Digital Systems and Hardware Description Languages.
Objectives
The main objective of the subject is to introduce the student in the design of mixed electronic systems:
- Learn the design and use of electronic systems on embedded system.
- Construction of electronic systems with FPGA/ASIC.
- Introduction to the hardware description from high-level languages.
Learning outcomes
- Construct, operate and manage systems for capture, transport, representation, processing, storage, management and presentation of multimedia information, in terms of electronic systems.
- Recognize hardware / software solutions for the implantation of electronic and telecommunication systems.
- Build hardware / software interfaces based on complex platforms.
- Exploit information and communication technology in observance of an engineer's ethical and professional responsibilities.
- Develop the capacity for analysis and synthesis.
- Develop scientific thinking.
- Manage available time and resources. Work in an organised manner.
- Work cooperatively.
- Assume and respect the role of the different members of a team, as well as the different levels of dependency in the team.
- Identify, manage and resolve conflicts.
- Adapt to multidisciplinary and international surroundings.
- Maintain a proactive and dynamic attitude with regard to one's own professional career, personal growth and continuing education. Have the will to overcome difficulties.
- Develop curiosity and creativity.
Contents
- Introduction: motivation of hardware description languages and synthesis of digital systems.
- System Verilog:
- Basic concepts.
- Combinational circuits.
- Sequential circuits.
- Creation of tests and verification.
- Computing resources: FIFOs, caches, multipliers and divisors, fixed-point and floating-point arithmetic.
- Synthesis of digital systems. Physical implementation (ASIC and FPGA).
- Advanced Digital Design:
- Multi-clock systems and clock domain crossing.
- Resets.
- Low-consumption techniques.
- Processors and Systems on Chip (SoC).
Learning activities and methodology
| Title | Hours | ECTS | Learning outcomes |
|---|---|---|---|
| Autonomous work | 80 | 3.2 | |
| Seminars | 12 | 0.48 | 1, 2, 3, 5 |
| Master classes | 26 | 1.04 | 1, 2, 3, 4, 5 |
| Laboratory classes | 12 | 0.48 | 7, 12 |
Theory classes:
Blackboard presentations of the theoretical part of the syllabus of the subject. The basic knowledge of the subject and indications of how to complete and deepen in the contents are given.
Problem seminars:
The scientific and technical knowledge presented in the master classes is worked on. Problems are solved and case studies are discussed. Problems promote the ability to analyze and synthesize, critical reasoning, and train the student in problem solving.
The methodology followed in problems is as follows: complete exercises are delivered that must be solved. In class, a review is made of the doubts that have arisen.
Laboratory classes:
The practices are carried out during the course and serve to deepen the practical knowledge of the subject.
The practices, whenever the capacity of the laboratory allows, will be carried out in groups of 2.
In the practices, the thinking habits specific to the subject and group work will be developed.
About the use of AI tools.
The use of AI tools helps learning. However, it is not allowed in any of the theoretical-practical activities that have an evaluation activity at the end.
Virtual tool
The Virtual Campus is used as a communication tool for the subject.
Assessment
Continuous assessment activities
| Title | Weight | Hours | ECTS | Learning outcomes |
|---|---|---|---|---|
| Theory | 60 | 8 | 0.32 | 1, 2, 3, 4, 5, 6, 7 |
| Laboratori classes | 40 | 12 | 0.48 | 8, 9, 10, 11, 12, 13 |
This subject/module does not provide for a single assessment system
The assessment of the subject is broken down into the following items:
Continuous assessment:
1. Continuous assessment tests. Continuous assessment tests have a weight between 55% and 60% in the final grade of the subject. The tests, among themselves, have the same weight. A minimum grade of 3.5 is required to be able to make an average in partial tests. Those who do not obtain this grade will be able to recover it in the final exam.
2. Laboratory activities. The weight in the total of the subject is between 35% and 40%. It is essential to pass the practices to pass the subject. There is no established mechanism for recovering practices. Attendance at practices is mandatory.
3. Carrying out exercises and other activities in class (if they are done, it is an optional assessment) can account for 10% of the final grade.
Final exam
There is a final assessment exam to recover the part(s) of the continuous assessment tests that have been failed.
Grade review procedure
For each assessment activity, a place, date and time of review will be indicated in which students can review the activity with the teacher. In this context, complaints may be made about the grade of the activity, which will be evaluated by the teacher responsible for the subject.
If the student does not attend this review, this activity will not be reviewed later.
Considerations
The grade of MH is given whenever the grade is greater than or equal to 90% of the total maximum grade for the subject and excellence is obtained in each of the assessment activities carried out.
Not evaluated indicates that no assessment activity has been carried out.
When one of the minimum grades specified for each assessment activity is not reached, a failure is obtained. The failure grade is calculated by applying a minimum of{4.5, average grade for the subject according to the weighting of activities}.
Irregularities committed
Without prejudice to other disciplinary measures that may be deemed appropriate, and in accordance with current academic regulations, irregularities committed by a student that may lead to a variation in the grade will be graded with a zero (0). For example, plagiarism, copying, allowing copying, unauthorized use of AI (e.g., Copilot, ChatGPT or equivalent) etc. in any of the assessment activities will imply failing it with a zero (0). Assessment activities graded in this way and by this procedure will not be recoverable. If it is necessary to pass any of these assessment activities to pass the subject, this subject will be directly failed, with no opportunity to recover it in the same course.
Repeating students
To receive differentiated treatment, the repeating student must send an email to the subject teacher at the beginning of the course. Each case will be studied in particular.
Any modification that may occur in this assessment forecast due to unforeseen circumstances will be communicated appropriately using the means of communication established at the beginning of the course.
Bibliography
Main bibliography:
S. Sutherland
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
CreateSpace Independent Publishing Platform
2017
V. Taraate
SystemVerilog for Hardware Description. RTL Design and Verification.
Springer
2020
M. Arora
The Art of Hardware Architecture. Design Methods and Techniques for Digital Circuits
Springer
2012
V. S. Chakravarthi
A Practical Approach to VLSI System on Chip (SoC) Design
Springer
2022
D. Harris
RISC-V System-on-Chip Design
Morgan Kaufmann
2026
Complementary bibliography:
M. Dalrymple
Microprocessor Design Using Verilog HDL
Circuit Cellar, Incorporated
2017
P. P. Chu
Embedded SoPC Design with NIOS II Processor and Verilog Examples
Wiley
2012
Software
Cadence and Altera developing tools are used for the laboratories.
Modelsim (Siemens) is used for modeling and simulation with SyetemVerilog
Course groups and languages
The information provided is provisional until November 30. After this date, you will be able to consult the language of each group through this link. To access the information, you will need to enter the course CODE
| Type of teaching | Group | Language | Semester | Shift |
|---|---|---|---|---|
| (TE) Theory | 320 | Catalan | first semester | morning-mixed |
| (PAUL) Classroom practices | 321 | Catalan | first semester | morning-mixed |
| (PLAB) Practical laboratories | 321 | Catalan/Spanish | first semester | morning-mixed |
| (PAUL) Classroom practices | 322 | Catalan | first semester | morning-mixed |
| (PLAB) Practical laboratories | 322 | Catalan/Spanish | first semester | morning-mixed |
| (PLAB) Practical laboratories | 323 | Catalan/Spanish | first semester | morning-mixed |
| (PLAB) Practical laboratories | 324 | Catalan/Spanish | first semester | morning-mixed |