
Digital Systems and Hardware Description Languages
Code: 102684Credits: 9
| Degree programme | Type | Course |
|---|---|---|
| Electronic Engineering for Telecommunications | OB | 2 |
| Telecommunication Systems Engineering | OB | 2 |
Contact lecturer
- Name :
- Mercedes Rullan Ayza
- Email :
- mercedes.rullan@uab.cat
Teaching staff
- Jordi Sacristan Gil
- Joaquín Saiz Alcaine
- Victor Montilla Gispert
Group languages
You can consult this information at the end of the document.
Prerequisites
There are no prerequisites. However, it is recommended for students to have previously taken the courses “Fundamentals of Computing” and “Theory of Circuis and Electronics”.
Objectives
This is a basic training course, taught during the second academic year, first semester. Is the bridge between the courses “Theory of Circuits and Electronics” and “Fundamentals of Computing”, in the first year, and “Computer Architecture and Peripherals”, in the second year.
The objective of the subject is for students to understand the role that digital systems play in the world of information technology and communications (ICT) in general, to be able to design and implement digital circuits of medium-low complexity using logic gates and reconfigurable devices and to understand that a computer is nothing more than a digital system of a certain complexity.
Methodologies based on “Processing Unit – Control Unit (UP-UC)” architectures are addressed to solve digital systems of a certain complexity, introducing the basic concepts of these architectures in both their “wired” version (UP-UC made with logic gates and blocks) and “microprogrammed” (UC based on ROM + sequencer).
In the third part of the subject, the basic concepts of computer architecture are presented and the design of an open source processor (RISC-V) is addressed based on its basic instruction repertoire and applying the design strategies and methodologies of the previous UP-UC architectures. Both the microprogrammed version (RVuabM) and the wired version (RVuabC) of this processor are implemented and the main differences in cost/performance of the two proposals are analyzed. We end up proposing a pipelined version (RVuabPL) as the optimal and most common solution used in current processors.
Learning outcomes
Electronic Engineering for Telecommunications
- KU117 (Distinguish the fundamentals of hardware description languages.) Distinguish the fundamentals of hardware description languages.
- KU118 (Describe the operation of combinational and sequential circuits, synchronous and asynchronous, microprocessors and integrated circuits.) Describe the operation of combinational and sequential circuits, synchronous and asynchronous, microprocessors and integrated circuits.
- SU120 (Design combinational and sequential, synchronous and asynchronous circuits and the use of microprocessors and integrated circuits.) Design combinational and sequential, synchronous and asynchronous circuits and the use of microprocessors and integrated circuits.
- SU121 (Use the fundamentals of software design, verification and validation to describe hardware systems based on high-level hardware description languages.) Use the fundamentals of software design, verification and validation to describe hardware systems based on high-level hardware description languages.
- SU122 (Use computer tools to search for bibliographic resources or information related to telecommunications and electronics.) Use computer tools to search for bibliographic resources or information related to telecommunications and electronics.
Telecommunication Systems Engineering
- KU117 (Distinguish the fundamentals of hardware description languages.) Distinguish the fundamentals of hardware description languages.
- KU118 (Describe the operation of combinational and sequential circuits, synchronous and asynchronous, microprocessors and integrated circuits.) Describe the operation of combinational and sequential circuits, synchronous and asynchronous, microprocessors and integrated circuits.
- SU120 (Design combinational and sequential, synchronous and asynchronous circuits and the use of microprocessors and integrated circuits.) Design combinational and sequential, synchronous and asynchronous circuits and the use of microprocessors and integrated circuits.
- SU121 (Use the fundamentals of software design, verification and validation to describe hardware systems based on high-level hardware description languages.) Use the fundamentals of software design, verification and validation to describe hardware systems based on high-level hardware description languages.
- SU122 (Use computer tools to search for bibliographic resources or information related to telecommunications and electronics.) Use computer tools to search for bibliographic resources or information related to telecommunications and electronics.
Contents
Block 1: Combinational Circuits (CC)
- Digital signals and digital systems. Description of digital systems. Electronic digital systems (EDS). MOS transistors. AND, OR and INV logical gates. Synthesis of EDS as a process of successive refinements.
- Combinational Circuits. Synthesis from a table I: ROM. Synthesis from a table II: logic gates.
- Boolean algebra. Truth tables.
- NAND, NOR, XOR, NXOR logical gates. 3-state buffers.
- Features: Propagation time. Hardware cost
- Other combinational blocks: multiplexers, decoders, AND-OR planes (PLAs).
- Synthesis tools: Synthesis from algorithms.
Block 2: Sequential Circuits (SC)
- The need for sequential circuits. Some examples. States and synchronization. Synchronous sequential circuits. Clock, reset and set.
- Explicit functional description of SCs. State transition graphs and tables.
- Basic components: Flip flops and latches.
- Synthesis of SC from tables. Moore and Mealy machines. States encoding.
- Registers, counters and memories. Structures, types and most common uses.
- Finite state machines (FSM). Formal definition. Implementation. Propagation times.
- Hardware description language: VHDL. Some examples of FSM description using VHDL.
- Sequential implementation of algorithms.
- Physical implementation of digital circuits. Field Programmable Gate Arrays (FPGA) and other implementation strategies.
Block 3: Process Unit-Control Unit (PU-CU) architecture and processors
- Processing Unit (PU) – Control Unit (CU) architecture.
- PU with multiplexers and with buses.
- Control Unit with a sequencer based on a ROM.
- Computer structure and fundamental concepts:
- Basic functional units (CPU, Memory, I/O, and Buses)
- Instruction set and types (machine-language programmer's perspective)
- Processor operation and basic addressing modes
- Von Neumann vs. Harvard and CISC vs. RISC architectures
- Design of an open-source RISC-V processor: from the instruction set (RV32I) to its implementation as a general-purpose UP-UC architecture:
- Microprogrammed implementation (RVuabM)
- Hardwired or single-cycle implementation (RVuabC)
- Pipelined version approach (RVuabPL)
Learning activities and methodology
| Title | Hours | ECTS | Learning outcomes |
|---|---|---|---|
| Laboratory practices | 18 | 0.72 | |
| Case study | 18 | 0.72 | |
| Preparing and solving exercises | 32 | 1.28 | |
| Laboratory practice assignments | 10 | 0.4 | |
| Videos viewing | 18 | 0.72 | |
| Exercise-based classes | 46 | 1.84 | KU117, KU118, SU120, SU121, SU122 |
| Autonomous work | 37 | 1.48 | |
| Preparing laboratory sessions | 30 | 1.2 |
The subject is ANNUAL and is organized into three conceptual blocks.
During the first semester, two-thirds of the subject will be taught (at PAUL level) during the 4 hours per week (and there are no practices). In the second semester, students will have to do all the practices (18 hours divided into 6 3-hour practices) and the remaining third of the subject (during 2 hours per week).
The materials offered through the Campus Virtual include a series of videos that student body must view before attending class and that contain the theoretical-practical knowledge needed for the design of digital systems, interactive self-correction exercises and a simulation environment. of digital systems.
The subject is taught in "classroom problems" mode. All face-to-face classes are treated as problem-based sessions. The classes are dedicated to solving questions and doubts in the videos, and cases proposed by the teacher. Student body must actively participate in these classes; these are not conventional "theory" classes. They take place in small groups (of the order of 40-50 students), an indispensable condition to reach the necessary degree of interactivity in a subject of eminently practical character.
The subject is completed with 6 laboratory practices. Normally and during the first session, the student carries out the work of simulation and validation of the designed circuits; in the second session, the design is overturned
FPGA to verify its real execution. Each session welcomes a maximum of 20-25 students who work in groups of 2 students and has a duration of 3 hours. The practices will take place in the second semester.
A design and simulation environment for programmable logic circuits Quartus II 13.0 sp1 Web Edition is used. The students become familiar with the concepts of capturing schemes, functional simulation, temporal simulation and with the description of simple digital systems using a hardware description language (System Verilog).
Tutoring sessions may be individual or in small groups and will be done on demand and in coordination between each teacher and the related students. There may also be open tutoring sessions for all interested students that may be proposed by the teaching staff; but these will require prior submission to the corresponding forum of the Virtual Campus (CV) those specific questions about concepts or exercises that must be addressed in order for the teachers to plan and carry out that tutoring properly.
Assessment
Continuous assessment activities
| Title | Weight | Hours | ECTS | Learning outcomes |
|---|---|---|---|---|
| Exercises delivering (periodic) | 20% | 8 | 0.32 | KU117, KU118, SU120, SU121 |
| Laboratory practices | 30% | 0 | 0 | SU122 |
| 3 partial test and/or final test | 50% | 8 | 0.32 | KU117, KU118, SU120, SU121 |
This course does not include single assessment.
a) Assessment activities
Student assessment includes the following activities:
- Three individual partial tests carried out face-to-face, in a controlled environment, and in written format. These partials tests assess the student's acquired knowledge and his/her skills designing efficient circuits and systems.
- Exercises resolution: a set of on-line exercises, with automatic grading, must be delivered on previously scheduled dates.
- The viewing of videos before attending the class.
- Activities in which students must demonstrate the skills acquired during the development of the practices.
Given that the subject is annual and that 2/3 of the subject will be taught during the first semester, 2 midterms will be held during the first semester on the dates planned for the degree (October and January); these two midterms will correspond to the grades PT1 and PT2.
Regarding the second semester (where there is 1/3 of the remaining subject and all the practices) a single midterm (PT3) will be held on the dates marked by the degree in June.
Finally, there will be a recovery corresponding to the 3 midterms on the dates planned for the degree in June/July; therefore in the first semester THERE WILL BE NO RECOVERY.
The mark of the course by continued assessment (CA) is obtained from:
- (activity 1) The mark obtained in the 3 partial tests (PT1, PT2, PT3)
- (activities 2 and 3) the delivery of exercises (both in the first and second four-month periods) and viewing of videos before attending the class (Pb),
- (activity 4) the mark of the laboratory activities (LT), and
according to the formula: CA = PT · 0.5 + LT · 0.3 + Pb · 0.2
where PT = (PT1+PT2+PT3)/3
To pass the course by continued assessment (CA) the following conditions must be met:
- CA ≥ 5
- PT1 and PT2 and PT3 must be ≥ 4, and PT must be ≥5, and
- LT must be ≥ 5
To reschedule an assessment activity at the UAB School of Engineering for justified reasons (serious medical, judicial or official reasons), a request for rescheduling of assessment activities can be made. This procedure must be carried out within the 5 calendar days prior to the test date or up to 5 calendar days after it.
b) Assessment activities: scheduling
Dates of the assessment tests and the submission of exercises are publishedin the Virtual Campus (VC) and may be subject to changes in programming due to unforeseen eventualities. Any modification will be reported through this platform.
It is important to bear in mind that no assessment activities will be permitted for any student at a different date or time to that established, unless for justified causes duly advised before the activity and with the lecturer’s previous consent. In all other cases, if an activity has not been carried out, this cannot be re-assessed.
c) Recovery process
The evaluation activity 1 corresponding to the theory can be recovered in the final test.
- If the grade obtained in one or two of the partial tests PT1, PT2 or PT3 is < 4, this grade must be exceeded by taking a retake exam in the corresponding block. In order to apply the formula (which takes into account the partial tests, the assessables and the practices), the grade obtained in this retake must be ≥ 5
- If the grade obtained in the 3 partial tests respectively is < 4, the student must take a new exam that will include the entire subject. The grade obtained will be the new PP grade, which must be ≥ 5 in order to apply the formula (which takes into account the partial tests, the assessables and the practices).
If PT < 5 or LT < 5 after retaking these new tests, the final score of the course will be the lowest number between CA and 4.5.
Activities 2 and 3 (delivery of exercises and viewing of videos before attending the class) which corresponds to 20% of the final grade and activity 4 (laboratory practices) which corresponds to 30% of the final grade cannot be recovered.
d) Grades review
Grades obtained by students in each test are published in the VC. Once the grades are published, students will be informed of the procedure to follow to review their exam. Students must request, through the VC, an exam review, and will receive a call with the day and time to do it through TEAMS.
Any student who does not follow this procedure, within the time frame established, may not request a new review.
e) Special grades
- A \"non-assessable\" grade cannot be assigned to students who have participated in any of the individual partial tests or the final test.
- In order to reach the qualification “with Honors”, the final grade must be ≥ 9.0. Because the number of students with this distinction cannot exceed 5% of the number of students enrolled in the course, this distinction will be awarded to whoever has the highest final grade.
f) Irregularities committed by the student, copy and plagiarism
Notwithstanding other disciplinary measures deemed appropriate, and in accordance with the academic regulations in force, assessment activities will receive a zero whenever a student commits academic irregularities that may alter such assessment. Assessment activities graded in this way and by this procedure will not be re-assessable. If passing the assessment activity or activities in question is required to pass the subject, the awarding of a zero for disciplinary measures will also entail a direct fail for the subject, with no opportunity to re-assess this in the same academic year.
Irregularities contemplated in this procedure include, among others:
- the total or partial copying of a test, practical exercise, report, or any other evaluation activity;
- allowing others to copy;
- presenting group work that has not been done entirely by the members of the group;
- unauthorized use of AI (eg Copilot, ChatGPT or equivalent) to solve exercises,practices and/or any other evaluable activity;
- presenting any materials prepared by a third part as one’s own work, even ifthese materials are translations or adaptations, including work that is not original or exclusively that of the student;
- having communication devices such as mobile phones, smart watches, etc., accessible during theoretical-practical in-class assessment tests (individual exams).
- talk to peers duringindividual theoretical-practical assessment tests (exams);
- copy or attempt to copy from other students during theoretical-practical assessment tests (exams); - use or attempt to use writings related to the subject during the performance of the theoretical-practical evaluation tests (exams), when these have not been explicitly allowed.
Prohibited use of AI:
For this subject, the use of Artificial Intelligence (AI) technologies is permitted exclusively in support tasks, such as bibliographic or information searches. The student must clearly identify which parts have been generated with this technology, specify the tools used and include a critical reflection on how these have influenced the process and the final result of the activity. The lack of transparency in the use of AI in this assessable activity will be considered a lack of academic honesty and may lead to a partial or total penalty in the grade of the activity, or greater sanctions in serious cases.
In future years of this course, students who have committed irregularities in an assessment will not have any of their completed assessment activities validated.
In short: cheating, allowing cheating, or plagiarizing (or attempting to) in any of the assessment activities is equivalent to a FAIL, which cannot be compensated and will not validate parts of the course in subsequent years.
g) Assessment of students who followed the subject last year but do not successfully passed it
Students who completed and passed the laboratory practices in the previous course but did not pass the course, may choose not to repeat them again during the current academic year. In that case, the laboratory practices grade (LT) will be 5, regardless of the grade reached the previous year.
The list of students who can choose this option will be published atthe beginning of the course in the VC. If, anyway, the student wants to make the laboratory practices again, he/she must communicate it by mail to the practice Coordinator.
If a student has committed irregularities (copies/plagiarism) in any evaluation activity in a previous call ofthe subject he willnot have the right to have his practices validated (if he had approved them).
Bibliography
- Course notes prepared by the teaching staff.
- Digital Design and Computer Architecture, RISC-V Edition. S. Harris, D. Harris. 1ª Edition 2021. Paperback ISBN 9780128200643; ebook ISBN 9780128200650
- The RISC-V Reader: An Open Architecture Atlas. D. Patterson, A. Waterman. ISBN-10, 0999249118. 2017
- Computer Organization and Design RISC-V Edition: The Hardware Software Interface. D.A. Patterson, J. L. Hennessy. 2021
- Digital Systems: From Logic Gates to Processors. Deschamps JP, Valderrama E, Terés L. Springer 2017. ISBN 978-3-319-41198-9.
- Coursera MOOC (español): https://www.coursera.org/learn/sistemas-digitales
- Coursera MOOC (inglés): https://www.coursera.org/learn/digital-systems
- Exercicis resolts de Disseny Digital. Joan Pons, Dani Bardés, Diego Mateo i Josep Altet. ISBN: 9798334549364. 1ª edició 2024.
- Complex Digital Systems. Deschamps JP, Valderrama E, and Terés L. Springer 2019. ISBN 978-3-030-12652-0.
Software
For the practical exercises, we will use Altera's FPGA software: Quartus II 13.0 SP1 Web Edition. Students will need to install this software, which does not require a license.
Course groups and languages
The information provided is provisional until November 30. After this date, you will be able to consult the language of each group through this link. To access the information, you will need to enter the course CODE
| Type of teaching | Group | Language | Semester | Shift |
|---|---|---|---|---|
| (PAUL) Classroom practices | 311 | Catalan | annual | morning-mixed |
| (PLAB) Practical laboratories | 311 | Catalan/Spanish | annual | morning-mixed |
| (PAUL) Classroom practices | 312 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 312 | Catalan/Spanish | annual | morning-mixed |
| (PAUL) Classroom practices | 313 | Catalan | annual | morning-mixed |
| (PLAB) Practical laboratories | 313 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 314 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 315 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 316 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 317 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 318 | Catalan/Spanish | annual | morning-mixed |
| (PLAB) Practical laboratories | 319 | Catalan/Spanish | annual | morning-mixed |
| (PAUL) Classroom practices | 511 | Catalan | annual | afternoon |